Transformations for functional verification of synthesized designs

A major problem with low-level functional verii-cation of any hierarchical system is the explosion of reachable states created when clocking mechanisms are incorporated into the model. These additional states make veriication more diicult, usually to the point that veriication at such a low level is not feasible. Transforms have been developed to take a nonhierarchi-cal model with a complex clocking mechanism and generate a provably equivalent model with a single clock. Furthermore, an algorithm has been developed to take a model with a complex clocking mechanism, described as a hierarchical network of modules, and generate a provably equivalent model with a single clock. These transformed models have a reduced state set and can be veriied in place of the original models in a fraction of the original time. This allows a synthesis system to generate simpler veriication models, while their results will be applicable to the original designs.